Electrical fuses are used to store address information for redundancy repair of high-density memories or other set-up information in memory or logic circuit components. In contrast to conventional laser fuses, electrical fuses can be set and reset even in packaged components. Such electrical fuses can be implemented with non-volatile memory cells using ferroelectric capacitors. Read out of such a ferroelectric capacitor memory cell typically requires a certain optimized “measurement” capacitance. In memory circuits, the parasitic bit-line capacitance is used for this purpose. In ferro fuse circuits, typically only one single cell is connected to the sense amplifier, i.e. no bit line or only a very short bit-line exists. Therefore, the bit-line capacitance is replaced by a gate oxide capacitance.
FIG. 1 shows a ferro fuse circuit 101 of the prior art. A ferroelectric capacitor (C1) 103 is connected to a plate (PL) 105 on one side and to a measurement capacitor (C2) 107 on the other side. By pulsing the plate (PL) 105, a read signal develops on a node F 109 depending on the stored polarization state in the capacitor C1103. If a “1” was stored in the ferroelectric capacitor C1103 then a bigger voltage is obtained on the node F 109 (switching). If a “0” was stored then a smaller voltage is obtained on the node F 109 (non-switching). These two voltage levels are compared to a reference voltage VREF 111 by a differential sense amplifier (SA) 113 and the fuse data is available on a node FD 115. As the read operation is destructive, a write back is required, which is performed automatically by the sense amplifier 113.
FIG. 2 shows another prior art ferro fuse circuit 201. The circuit 201 uses two cells like the cell 101 in FIG. 1 are combined to store one single data bit. Two ferroelectric capacitors C1203 and C3204 are connected to a plate (PL) 205 on one side and to measurement capacitors C2207 and C4208 on the other. The two ferroelectric capacitors C1203 and C3204 always contain reversed data (i.e. if a “1” signal is obtained on a node F 209 then a “0” signal is obtained on a node /F 210, and visa versa). Thus the differential signal between the nodes F 209 and /F 210 is doubled compared to the implementation of FIG. 1. Fuse data output from a sense amplifier 213 is available on a node FD 215. Furthermore, no reference voltage is required. However, in the implementation of FIG. 2, the area for storage and measurement capacitors is doubled.
It would be desirable to produce a ferro fuse having a large signal margin.